Job Description

Minimum qualifications: + Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. + 10 years of experience in high-performance CPU, cache subsystem or AI accelerator logic/RTL design including microarchitecture definition and PPA optimizations. + 10 years of experience in CPU-centric arithmetic dataflow design. + 6 years of experience leading and managing teams for modern processor subsystems with high speed, lower power design. Preferred qualifications: + Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, or a related field. + Experience with ARM Instruction Set Architecture. + Experience with mobile CPU subsystem and SOC architecture/integration. + Experience with front-end quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, UPF, and Low Power Optimization/Estimation). Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will contribute to all phases of complex designs of CPU subsystems from design specification to productization, including integration into SOCs. You will lead and manage a front-end design team, collaborate with members of architecture, software, verification, power, DFT, physical design teams to define the microarchitecture and schedule in delivering high-quality RTL that meets project goals. You will help your team grow and solve technical problems with innovative micro-architecture and practical logic solutions. You will be responsible for evaluating and deciding on the best design options with complexity, performance, power and area and schedule in mind. The US base salary range for this full-time position is $227,000-$320,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google ( . + Lead and manage a team of design engineers working on CPU, cache subsystem, or Artificial Intelligence (AI) accelerator design and integration into SOC, emphasizing on microarchitecture and Register-Transfer Level (RTL) design for the next generation CPU subsystem. + Review performance enhancing microarchitecture features, and work with Software, Architect and Performance teams for trade-off studies. Communicate the pros and cons of microarchitecture enhancements. + Deliver with plans on achieving project milestones and goals, towards a design that meets production quality on schedule. + Work with the Verification team to ensure production of quality designs, and the physical design and power teams to meet frequency, power, and area goals. + Focus on floating point/vector/SIMD/matrix dataflow pipeline design, and optimizations with other parts of the CPU to deliver the best Power Purchase Agreement (PPA). Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also and If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form:

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Full time, Worldwide,

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