Job Description

**Job Role: Senior** **Mixed Signal DV Engineer** **Job Location: San Jose CA** **Job description:** We are seeking Mixed Signal DV Engineer who will extract modeling specifications from designers and will be involved in development of Analog/Mixed-Signal model in System-Verilog, development of UVM Testbench and developing test cases and run simulation and fix the behavioral model working with Circuit designer. They will also develop timing model for the circuit working with layout engineer. **Key responsibilities:** + This role will provide the ability to directly influence design related changes as required to meet functional specifications. + Determine whether anomalous symptoms are caused by errors in the specifications, models, testbench, or design. + Support integration of composite models into larger composite models maintained by other groups. **Required Skills** + AMS Verification, UVM/System Verilog, Python, Synopsys/Cadence EDA Verifications Tools. + Good knowledge of System-Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc. + Good understanding of digital design for mixed signal control loops and designing Verilog / Verilog- A code to control analog circuits (e.g. bandgap, PLL, Amplifier, Filters, CDR.,). + Familiarity with behavioral Verilog code for an analog circuit. + Ability to write detailed test benches for digital and AMS simulators. + Deep understanding of constraints, especially for mixed-signal designs, including multiple clock domains and clock gating. + Familiarity with timing closure and static timing analysis tools. + Experience with scan chain vector generation and verification. **Life at Capgemini** Capgemini supports all aspects of your well-being throughout the changing stages of your life and career. For eligible employees, we offer: + Flexible work + Healthcare including dental, vision, mental health, and well-being programs + Financial well-being programs such as 401(k) and Employee Share Ownership Plan + Paid time off and paid holidays + Paid parental leave + Family building benefits like adoption assistance, surrogacy, and cryopreservation + Social well-being benefits like subsidized back-up child/elder care and tutoring + Mentoring, coaching and learning programs + Employee Resource Groups + Disaster Relief **About Capgemini Engineering** World leader in engineering and R&D services, Capgemini Engineering combines its broad industry knowledge and cutting-edge technologies in digital and software to support the convergence of the physical and digital worlds. Coupled with the capabilities of the rest of the Group, it helps clients to accelerate their journey towards Intelligent Industry. Capgemini Engineering has 65,000 engineer and scientist team members in over 30 countries across sectors including Aeronautics, Space, Defense, Naval, Automotive, Rail, Infrastructure & Transportation, Energy, Utilities & Chemicals, Life Sciences, Communications, Semiconductor & Electronics, Industrial & Consumer, Software & Internet. Capgemini Engineering is an integral part of the Capgemini Group, a global business and technology transformation partner, helping organizations to accelerate their dual transition to a digital and sustainable world, while creating tangible impact for enterprises and society. It is a responsible and diverse group of 340,000 team members in more than 50 countries. With its strong over 55-year heritage, Capgemini is trusted by its clients to unlock the value of technology to address the entire breadth of their business needs. It delivers end-to-end services and solutions leveraging strengths from strategy and design to engineering, all fueled by its market leading capabilities in AI, generative AI, cloud and data, combined with its deep industry expertise and partner ecosystem. The Group reported 2024 global revenues of 22.1 billion. Get the future you want | **Disclaimer** Capgemini is an Equal Opportunity Employer encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law. This is a general description of the Duties, Responsibilities and Qualifications required for this position. Physical, mental, sensory or environmental demands may be referenced in an attempt to communicate the manner in which this position traditionally is performed. Whenever necessary to provide individuals with disabilities an equal employment opportunity, Capgemini will consider reasonable accommodations that might involve varying job requirements and/or changing the way this job is performed, provided that such accommodations do not pose an undue hardship. Capgemini is committed to providing reasonable accommodations during our recruitment process. If you need assistance or accommodation, please reach out to your recruiting contact. Please be aware that Capgemini may capture your image (video or screenshot) during the interview process and that image may be used for verification, including during the hiring and onboarding process. Click the following link for more information on your rights as an Applicant Applicants for employment in the US must have valid work authorization that does not now and/or will not in the future require sponsorship of a visa for employment authorization in the US by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Mixed-Signal Design Verification Engineer_ **Location:** _CA-San Jose_ **Requisition ID:** _078939_

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Flexible hours,

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